Volume 2 - Issue 3, May - June 2026

This paper introduces a novel protocol verification method for the Advanced Peripheral Bus (APB) protocol using SystemVerilog. The microprocessor technology and System-on-Chip (SoC) architectures are advancing day by day, so an effective interface between the high-speed devices on the board and comparatively low-speed components is essential for superior performance. Hence, interconnects have a significant role in SoC design. SoCs mostly employ APB on-chip communication protocol to connect lowbandwidth peripherals because APB is a simple and low-power bus protocol. Additionally, functional verification has been recognized as a crucial step in the design cycle since it ensures the proper functioning of APB-based designs. This work establishes an efficient way to verify APB protocol functionality by developing a structured environment that leverages the additional features of SystemVerilog over Verilog specifically intended for verification. The testbench components of SystemVerilog, such as interface, driver, monitor, scoreboard, and assertions, generate a functional coverage report. Simulation results demonstrate that the APB design operates correctly under different test scenarios, ensuring reliable communication between the master and slave components.

Piali Chakraborty, Syed Lukhman, Tejas K Y,"APB Verification Using SystemVerilog" International Journal of Advanced Multidisciplinary Research and Educational Development, V2(3): Page(1335-1342) May-June 2026. ISSN: 3107-6513. www.ijamred.com. Published by Scientific and Academic Research Publishing.