Volume 2 - Issue 2, March - April 2026

Static Random Access Memory (SRAM) is an essential element in current digital systems which is extensively utilized in cache memory and low power applications owing to its high-speed and reliability features. With the development of the CMOS technology, the amount of leakage power has turned into one of the most dominant factors causing total power dissipation, especially at standby mode. This paper focuses on designing and implementation of a low power 32x32 SRAM memory array by applying the power gating scheme in order to overcome the leakage power issue. The proposed architecture is comprised of conventional 6T SRAM cells along with sleep transistors capable of turning off power to the memory arrays during stand-by mode. In order to validate the performance of the proposed circuit, Tanner EDA software packages such as S-Edit for schematic drawing and T-Spice for simulation are employed. The comparison between the proposed and traditional designs reveals that the power consumption is considerably decreased from 2.615 µW to 1.7402 µW while increasing the number of transistors slightly.

Dr.Katragadda Swarnasri, Asanapuram Vasantha, Kandagunta Tirumala Rao, Karri Udaya Sri, Devarakonda Varshitha Joy,"Design and Implementation of 32 x 32 SRAM for Low Power Applications" International Journal of Advanced Multidisciplinary Research and Educational Development, V2(2): Page(1453-1460) Mar-Apr 2026. ISSN: 3107-6513. www.ijamred.com. Published by Scientific and Academic Research Publishing.